FIELD OF THE INVENTION
The invention relates to an integrated semiconductor memory having a redundant device with normal memory cells, which are arranged in a matrix at intersections of word lines and bit lines, word line decoders for selecting a word line as a function of word line address signals which are applicable to the semiconductor memory, bit line decoders for selecting a bit line as a function of bit line address signals which are applicable to the semiconductor memory, external reading and evaluator circuits associated with the bit lines of the normal memory cells and connected on an output side thereof with data lines at which data content to be read out of the normal memory cells is to be output, and redundant memory cells which, by means of at least one programmable redundant decoder, are addressable for replacing a defective memory cell.
In modern integrated semiconductor memories, memory cells are disposed in a plurality of memory field block units. In operation, to save electric current and time, as a rule, only one memory field block unit is activated at any one time as a function of address signals. To increase the yield when these semiconductor memories are manufactured, it has become known to provide redundant lines with redundant memory cells along the redundant lines. In operation, when necessary or, in other words, when redundant memory cells are intended to replace normal memory cells ("redundant case"), the redundant lines are triggered instead of the normal lines. This is effected via so-called redundant decoders, which are programmable to the address of the respective normal line having the defective memory cells to be replaced.
FIG. 5 shows schematically a heretofore known and used integrated semiconductor memory 1 having a redundant device 2. The memory 1 includes normal memory cells, which are arranged in a matrix at intersections of word lines and bit lines 3,4, which are not otherwise illustrated in detail; the bit lines are organized in a conventional manner pairwise in bit lines 3 and complementary bit lines 4, and pairwise have internal reading circuits which are arranged in the cell matrix of the memory cells but are not shown in detail in FIG. 5, each bit line 3,4 typically including two halves, one of which is disposed on the right-hand side in FIG. 5 and the other on the left-hand side of the figure. Otherwise nonillustrated word line decoders are provided for selecting a word line as a function of word line address signals which are applicable to the semiconductor memory, and bit line decoders 5 are provided to select a bit line 3,4 as a function of bit line address signals which are applicable to the semiconductor memory; in a conventional manner, the bit line decoders 5 are preceded by bit line precharging devices 6, by means of which the bit lines 3,4 are charged to a precharge potential before the data are read out. At one input of the bit line precharge device 6 is a signal AIC (=address input column), from which column address signals are derived for triggering the bit line decoder 5. At the output of the bit line decoder 5 are column select signals CSLS which, in a conventional manner, are supplied to activate switches 7 for selecting the bit lines 3,4. Also assigned to the bit lines 3,4 of the normal memory cells are external reading and evaluator circuits 8 (generally known as read amplifiers) which are disposed outside the cell matrix and connected on the output side with data lines DL0, DL1, DL2, DL3, at which the data contents to be read out of the normal memory cells are output, and on the input side with external bit lines BE0, BE1, BE2, BE3 and complementary lines thereof, also known as I/O lines. The memory 1 also has redundant memory cells (not otherwise shown in detail), which are addressable for replacing a defective memory cell by means of a programmable redundant decoder 9. To that end, the redundant decoder 9 has a programming device, which is otherwise not shown in detail, assigned thereto for programming a column address of the redundant memory cells; this programming device having conventional fuse elements which can be interrupted by the action of light or electric current. The redundant decoder 9, at an output side thereof at which the column address signal AIC is also located, on the one hand, outputs a redundance inhibit signal REDINH for controlling the bit line pre-charge device 6, and, on the other hand, a redundant selection signal RED for triggering switches 10, which enable the selected redundant bit lines 11 and redundant bit lines 12 complementary thereto to be connected with the reading circuits 8 so that, in the redundant case, the data contents of the redundant memory cell (not shown in further detail), instead of the normal memory cell, can be output to the data lines DL0 to DL3.
From the schematic diagram of FIG. 1, illustrating the chronological sequence of redundance provisions in a heretofore known or prior-art semiconductor memory in use, a disadvantage of the mode of operation of the known redundant device is explained hereinafter in connection with FIG. 5. In the redundant case, it is necessary for the decoding of the normal bit lines 3,4 to be blocked, so that an unambiguous redundant bit line signal can be read out by the external reading and evaluator circuits 8. Because the redundant bit lines 11,12 are connected, together with the normal bit lines 3,4, to the same external reading and evaluator circuits 8, and therefore only data from normal memory cells or only data from redundant memory cells can ever be read out, the bit line decoder 5 or the bit line precharge device 6 must be enabled by the redundant decoder 9 if it is to be possible for the data to be read out of normal memory cells.
The conventional or heretofore known arrangement of a redundant device also has the disadvantage that in each individual memory field block unit, only at most as many normal bit lines as there are redundant bit lines of such a memory field block unit can be replaced by redundant bit lines. Each memory field block unit is understood to be a unit having a eight arrays and memory cell blocks, respectively, of memory cells, which are activatable and operatable independently of one another in a conventional manner. In the operation of such a semiconductor memory, not all of the units are operated simultaneously; rather, only some of the memory field block units or operated at any one time. To that end, each memory field block unit can be selected by means of a block selection signal associated with the particular memory field block unit. The selection is effected by means of a block decoder, not shown in further detail, which is controlled by a first portion of the word line address signals (and signals complementary thereto), all of the memory field block units being activated simultaneously. In actual practice, this can mean that such a semiconductor memory contains more normal bit lines with defective memory cells in a memory field block unit than redundant bit lines with suitable redundant memory cells in that same memory field block unit. Hence, such a memory cannot be repaired using the redundant architecture known heretofore, even though there may still be enough redundant bit lines with redundant memory cells in other memory block units than the memory field block units under consideration, which are not being used in these other memory field block units.